1. Field of the Invention
The present invention relates to network interface devices for interconnecting host processors with a communication network, and more particularly to the processing of specific types of packets using high speed, and/or embedded hardware at the network interface.
2. Description of Related Art
Network interface cards (NIC) are often be used for network connection between a host bus system and a network medium. NICs have integrated circuits with buffer memory for storing packets in transit. For outgoing traffic, the packets being downloaded from host memory via the host bus system go through a transmit packet data buffer and medium access control MAC unit to be transmitted onto the wire, optical fiber, or antenna (or otherwise transmitted on a network medium). For incoming traffic, the packet being received from the network medium can go through the MAC unit and a receive packet data buffer to be uploaded into host memory.
There are times that the packets can be processed on the NIC, rather than after delivery to other processing resources. For example, in embedded firewall applications, a certain field, or fields, of the packet can be inspected to determine whether further transfer of the packet should be allowed or denied.
Management of computer networks is accomplished in many systems by a central network management station which has access to end stations in the network for management functions. Several specialized control packets have been developed, which are transmitted to the end stations in support of these management functions. Some of these control packets are suitable for processing, or are designed to be processed, at the network interface, rather than after delivery to the host system on which the network interface is attached.
In one prior art system, network interface devices are configured to capture packets while the host system is not active, including “wake up” packets using resources on the interface card. See, NIC Device-Class Power Management Specification, Version 1.0a, Nov. 21, 1997; Microsoft Corporation. (See, http://www.microsoft.com/hwdev/specs/PMref/PMnetwork.htm). The NIC Device-Class Power Management Specification handles the situation in which a host processor running Windows or another operating system OS wants to go to sleep, yet allow others to access any shared directories or devices it might have offered to the network. So the host OS passes the adapter a set of filters (where a filter in this example is a bit mask to specify which bytes in the packet are interesting, with a byte string for comparing with the interesting bytes) which the adapter should use. If a packet comes in that matches the filters, then the adapter wakes up, and signals power management resources in the host system.
Also, inspection of a field or fields in a packet may be required in support of logical processing of the packet for priority determinations, or other network management and system management functions.
In other examples, the packets processed on the NIC include a remote control packet allowing a management console to remotely reboot the targeted computer. Such a packet would simply be discarded by the interface processor and an action performed to reboot the computer, such as by sending a command to the host using a management interface like the SMBus (See, Smart Battery System Specifications—System Management Bus Specification, Rev. 1.0, (1995) Benchmarq Microelectronics, Inc., et al.).
In yet another example of NIC based packet processing, NIC might execute processes for which it needs to know the local internet protocol IP address of its host. This can be complicated if Dynamic Host Configuration Protocol DHCP, or another protocol for assigning dynamic IP addresses to devices on a network, is in use by which the IP address might change over time. By trapping the DHCP packets and examining them before passing them to the host, the interface card can track the changes in the IP address as they happen, and do it without adding any extra instructions to the critical code paths on the host which might increase CPU utilization or reduce performance.
In the prior art, to process data in a packet, the processing resources on the MC have been required to read several fields in the packet in order to identify fields relevant to the processing being executed. For example, TCP/IP packets have certain fields that have a pre-specified location in the packet based on the layer two protocol. However, the IP header and TCP header have variable lengths. So in order to find the start of the TCP header, the NIC must first find the start of the IP header, and the length of the IP header to calculate the variable location of the start of the TCP header. Accordingly, packet processing requires multiple read and-process cycles, which make it more difficult to keep up with the packet throughput in the NIC. Therefore, there is a chance that the buffer memory in the NIC will overflow, while processing resources on the NIC process a particular packet. If the memory overflows, packets are dropped and network performance suffers.
With 100 Megabit, Gigabit and higher wire speeds, it becomes even more difficult for the processor to inspect the packets, especially for small size packets. See, International Patent Publication No. WO01/37489 Al, entitled RECEIVE FILTERING FOR COMMUNICATIONS INTERFACE, invented by Connery, et al., published on 25 May 2001, (priority based on U.S. patent application Ser. No. 09/434,253) which describes techniques for improving performance of processor-based inspection of data packets in transit through a NIC, by reducing the number of packets that must be processing in the packet flow.
It is desirable to provide a network interface capable of processing packets, without incurring the increased costs associated with higher speed, powerful on chip, or on-board, processors. Also, it is desirable to extend the type of processes that may be executed by resources at the network interface.